1. Field of the Invention
The present invention relates to a structure of a semiconductor device, and more particularly, to a thin film transistor (TFT) and a pixel structure with the thin film transistor.
2. Description of the Related Art
A thin film transistor liquid crystal display is composed of a thin film transistor array substrate, a color filter array substrate and a liquid crystal layer, wherein the thin film crystal transistor array substrate is composed of many thin film transistors arranged in an array and pixel electrodes corresponding to each thin film transistor to form pixel structures. The thin film transistor mentioned above includes a gate electrode, a channel layer, a source region and a drain region which is adapted to serve as a switch for a liquid crystal display element. However, the typical pixel structure has overlap shift issue as shown in FIGS. 1A and 1B.
FIGS. 1A and 1B are schematic top views of pixel structures without overlap shift and with overlap shift issues in accordance with the prior art respectively. Referring to FIG. 1A, a schematic top view of a pixel structure 100 without overlap shift in accordance with the prior art is shown. The pixel structure 100 comprises a gate electrode 102, a scan line 104, a gate dielectric layer (not shown), a channel layer 106, a source region 108, a drain region 110, a data line 112, a protection layer (not shown) and a pixel electrode 114. The scan line 104 is electrically connected to the gate electrode 102 and formed on a substrate (not shown), wherein the scan line 104 and the gate electrode 102 are formed from a first metal layer. The gate dielectric layer covers the scan line 104 and the gate electrode 102. In addition, the channel layer 106 is formed over the gate dielectric layer formed over the gate electrode 102, and the source region 108 and the drain region 110 are formed on the gate dielectric layer beside the gate electrode 102. The source region 108 and the drain region 110 partially overlap the channel layer 106, wherein the source region 108 and the drain region 110 are formed using a second metal layer. Moreover, the data line 112 is formed over the gate dielectric layer and electrically connected to the source region 108, wherein the data line 112 is also formed using the second metal layer. The gate electrode 102, the channel layer 106 and source region 108 and the drain region 110 respectively constitutes a thin film transistor 120. The protection layer is formed over the thin film transistor 120, the scan line 104 and the data line 112, wherein the protection layer has a contact 116 to expose the drain region 110. The pixel electrode 114 is electrically connected to the drain region 110 through the contact 116.
In the pixel structure mentioned above, a parasitic capacitance Cgd(a) within the gate electrode 102 and the drain region 110 depends on the overlap area of the gate electrode 102 and the drain region 110. If the parasitic capacitance within the gate electrode 102 and the drain region 110 changes, the performance of a liquid crystal display will be affected therefrom.
The main cause of changing the parasitic capacitance within the gate electrode and the drain region results from the misalignment of the first metal layer, i.e. the gate electrode, and the second metal layer, i.e. the source/drain regions, as shown in FIG. B. In comparison with FIG. 1A, the second metal including the data line 112, the source/drain regions 108 and 110, respectively, shown in FIG. 2B shifts; therefore, the parasitic capacitance Cgd(a) within the gate electrode 102 and the drain region 110 varies with the overlap area of the gate electrode 102 and the drain region 110 as to generate mura effects.